1. Field of the Invention
The present invention relates to bus controllers for controlling bus transfers between a host device and a slave device and more particularly to such a bus controller where a slave bus may have a variable width.
2. Background of the Invention
Since their introduction in the 1970's, microprocessors have advanced from 4, to 8, to 16 to 32-bit devices. In the not-too-distant future, 64 and 128-bit devices are expected to become commonplace. In order to maintain downward compatibility with previous-generation hardware and software, later generation devices must provide some flexibility in data transfer. An example of how such flexibility has been achieved in the past is provided by the Intel 80386 and 80486 microprocessors. The 386/486 processors are designed such that bus operands may be bytes (8-bits) words (16-bits) or double words (32-bits). In place of the two least significant address bits A0 and A1, the processor generates four byte enable signals BE0, BE1, BE2 and BE3, indicating which portion of the processor bus takes place in a particular transaction. For example, if the pattern of byte enable signals (which are active low) were 1110, only data lines D0-D7 would participate in the bus transaction. If the byte enable pattern were 1100, data lines D0-D15 would participate in the bus transaction.
Implicit in the byte enable pattern is the size of the operand being transferred. In the former example, the operand is a byte, and in the latter example, the operand is a word. Since the operand must be a byte, word, or double word, byte enable patterns in which two active byte enable bits are separated by one or more inactive byte enable bits do not occur. That is, the byte enable patterns are divided into a "legal" set and an "illegal" set. Further in accordance with the foregoing arrangement, a word operand is said to be aligned in memory if its address is a multiple of two, and a double word operand is said to be aligned in memory if its address is a multiple of four. A byte operand is always aligned. The data transfer mechanism does not require operand alignment. In the case of unaligned operands, however, multiple bus cycles may be required to complete the transfer of the operand. These multiple bus cycles are automatically generated by the microprocessor.
With the prevalence of graphical user interfaces, increasing reliance is being placed on graphics coprocessors to speed up graphics operations. One way in which a graphic coprocessor can speed up performance is to merge memory requests from the CPU when possible in order to increase data transfer efficiency. Request merge operations can cause "legal" byte enable patterns produced by the CPU to be altered in such a way as to produce modified "illegal" byte enable patterns. The 386/486 data transfer model then becomes unsuitable.
The present invention provides a dam transfer mechanism that overcomes the foregoing difficulty. The invention may be used to particular advantage in a PC graphics environment. More specifically, it may be used within a graphics coprocessor to realize a VGA-compatible 32/16/8 bus controller.